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IEICE Trans

Takuya IWAKAMI

An Instruction Mapping Scheme for FU Array Accelerator
Kazuhiro YOSHIMURA Takuya IWAKAMI Takashi NAKADA Jun YAO Hajime SHIMADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/02/01
Vol. E94-D  No. 2  pp. 286-297
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
instruction mapping, FU array, coarse-grained reconfigurable architecture, 
 Summary | Full Text:PDF