An Instruction Mapping Scheme for FU Array Accelerator

Kazuhiro YOSHIMURA  Takuya IWAKAMI  Takashi NAKADA  Jun YAO  Hajime SHIMADA  Yasuhiko NAKASHIMA  

IEICE TRANSACTIONS on Information and Systems   Vol.E94-D   No.2   pp.286-297
Publication Date: 2011/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E94.D.286
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
instruction mapping,  FU array,  coarse-grained reconfigurable architecture,  

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Recently, we have proposed using a Linear Array Pipeline Processor (LAPP) to improve energy efficiency for various workloads such as image processing and to maintain programmability by working on VLIW codes. In this paper, we proposed an instruction mapping scheme for LAPP to fully exploit the array execution of functional units (FUs) and bypass networks by a mapper to fit the VLIW codes onto the FUs. The mapping can be finished within multi-cycles during a data prefetch before the array execution of FUs. According to an HDL based implementation, the hardware required for mapping scheme is 84% of the cost introduced by a baseline method. In addition, the proposed mapper can further help to shrink the size of array stage, as our results show that their combination becomes 88% of the baseline model in area.