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IEICE Trans

Takashi IWAMOTO

Hardware Framework for Accelerating the Execution Speed of a Genetic Algorithm
Barry SHACKLEFORD Etsuko OKUSHI Mitsuhiro YASUDA Hisao KOIZUMI Katsuhiko SEO Takashi IWAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 962-969
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multi Processors
Keyword: 
genetic algorithm, special purpose hardware architecture, combinatorial optimization, 
 Summary | Full Text:PDF