Hisao KOIZUMI


Synthesis of Minimum-Cost Multilevel Logic Networks via Genetic Algorithm
Barry SHACKLEFORD Etsuko OKUSHI Mitsuhiro YASUDA Hisao KOIZUMI Katsuhiko SEO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2528-2537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
genetic algorithmlogic synthesishardware acceleration
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A Proposal of a Method of Total Quality Evaluation in Remote Conference Systems Based on ATM Networks
Nobuhiro KATAOKA Hisao KOIZUMI Hideru DOI Kenichi KITAGAWA Norio SIRATORI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/09/25
Vol. E81-B  No. 9  pp. 1709-1717
Type of Manuscript:  PAPER
Category: Communication Networks and Services
Keyword: 
ATMremote conferenceQoSmultimedia networkconference quality
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A Method for Design of Embedded Systems for Multimedia Applications
Katsuhiko SEO Hisao KOIZUMI Barry SHACKLEFORD Masashi MORI Takashi KUSUHARA Hirotaka KIMURA Fumio SUZUKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 725-732
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
co-verificationco-designco-simulationco-emulationembedded systemcomponent logical bus
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Embedded System Cost Optimization via Data Path Width Adjustment
Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10  pp. 974-981
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High Level Synthesis
Keyword: 
embedded systemssystem on chipCPUmemory
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Top-Down Co-simulation of Hardware/Software Co-designs for Embedded Systems Based Upon a Component Logical Bus Architecture
Katsuhiko SEO Hisao KOIZUMI Barry SHACKLEFORD Mitsuhiro YASUDA Masashi MORI Fumio SUZUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10  pp. 1834-1841
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
co-designco-simulationembedded systemcomponent logical bus
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Hardware Framework for Accelerating the Execution Speed of a Genetic Algorithm
Barry SHACKLEFORD Etsuko OKUSHI Mitsuhiro YASUDA Hisao KOIZUMI Katsuhiko SEO Takashi IWAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 962-969
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multi Processors
Keyword: 
genetic algorithmspecial purpose hardware architecturecombinatorial optimization
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Satsuki: An Integrated Processor Synthesis and Compiler Generation System
Barry SHACKLEFORD Mitsuhiro YASUDA Etsuko OKUSHI Hisao KOIZUMI Hiroyuki TOMIYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10  pp. 1373-1381
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Hardware-Software Codesign
Keyword: 
computer aided designsystem designprocessor designcompiler generation
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A Proposal for a Co-design Method in Control Systems Using Combination of Models
Hisao KOIZUMI Katsuhiko SEO Fumio SUZUKI Yoshisuke OHTSURU Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3  pp. 237-247
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: System Design
Keyword: 
co-designmodelingvirtual instrumentreplacement method
 Summary | Full Text:PDF