Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2023/09/01 Vol. E106-ANo. 9pp. 1082-1091 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Algorithms and Data Structures Keyword: enumeration algorithm, reverse search, simple polygon, empty polygon, surrounding polygon,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2021/09/01 Vol. E104-ANo. 9pp. 1101-1107 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Algorithms and Data Structures Keyword: algorithms, dispersion problem, facility location,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2018/09/01 Vol. E101-ANo. 9pp. 1420-1430 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: cube, net, polyomino, pythagorean triple, rep-cube, rep-tile,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2018/09/01 Vol. E101-ANo. 9pp. 1363-1374 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: graph algorithm, graph partitioning, decision diagram, frontier-based search, enumeration problem,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/06/01 Vol. E97-ANo. 6pp. 1206-1212 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: GeoLoop, hinged dissection, Ivan's Hinge, NP-hardness, paper folding,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/03/01 Vol. E96-DNo. 3pp. 399-399 Type of Manuscript: FOREWORD Category: Keyword:
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-ANo. 12pp. 2472-2480 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: automatic clock gating generation, low power, dynamic power reduction, BDD,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-ANo. 12pp. 3531-3538 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: power gating, multi-threshold CMOS (MTCMOS) technology, BDD, controlling value, leakage power reduction,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-ANo. 9pp. 2301-2307 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: Hajos calculus, planar graph, coloring, proof systems,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-ANo. 12pp. 3427-3434 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: HDL, high-level synthesis, bit-length optimization, non-linear programming,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-ANo. 12pp. 3184-3191 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic and High Level Synthesis Keyword: HDL, high-level synthesis, parallelizing compiler, bit length,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-ANo. 12pp. 2701-2707 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: field programmable gate array (FPGA), LUT architecture, reconfigurable logic,