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IEICE Trans

Takahiro KAWAGUCHI

32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor
Takahiro KAWAGUCHI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2022/06/01
Vol. E105-C  No. 6  pp. 245-250
Type of Manuscript:  INVITED PAPER (Special Section on Progress & Trend of Superconductor-based Computers)
Category: 
Keyword: 
SFQ digital circuit, ALU, wide datapath circuit, bit-parallel processor, clockless gate, 
 Summary | Full Text:PDF
A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model
Takahiro KAWAGUCHI Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2556-2564
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
single-flux-quantum circuit, static timing analysis, formal verification, 
 Summary | Full Text:PDF