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IEICE Trans

Tai-Ping WANG

An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing
Tong-Yu HSIEH Tai-Ping WANG Shuo YANG Chin-An HSU Yi-Lung LIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/03/01
Vol. E99-C  No. 3  pp. 404-414
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
low-pin count testing, multi-site testing, test cost, scalability, ATE utilization, 
 Summary | Full Text:PDF
Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders
Ming-Der SHIEH Tai-Ping WANG Chien-Ming WU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/09/01
Vol. E91-D  No. 9  pp. 2300-2311
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
Viterbi decoder (VD), in-place scheduling, path metric memory management, VLSI architecture, 
 Summary | Full Text:PDF