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IEICE Trans

Shoji WADA

A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age
Yuji SAKAI Kanji OISHI Miki MATSUMOTO Shoji WADA Tadamichi SAKASHITA Masahiro KATAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7  pp. 782-788
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
DRAM, synchronous operation, memory, 
 Summary | Full Text:PDF
High Speed Data Output Circuit Techniques for a 17 ns 4 Mbit BiCMOS DRAM
Hitoshi MIWA Shoji WADA Yuji YOKOYAMA Masayuki NAKAMURA Tatsuyuki OHTA Toshio MAEDA Masahiro YOSHIDA Hideuki MIYAZAWA Noboru AKIYAMA Kazuyuki MIYAZAWA Jun MURATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11  pp. 1344-1350
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
BiCMOS, noise immune, data sense, level shift, 
 Summary | Full Text:PDF