A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age

Yuji SAKAI  Kanji OISHI  Miki MATSUMOTO  Shoji WADA  Tadamichi SAKASHITA  Masahiro KATAYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.7   pp.782-788
Publication Date: 1995/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
DRAM,  synchronous operation,  memory,  

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Summary: 
As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of the DRAM and its new pipeline architecture.