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IEICE Trans

Shinsuke KOBAYASHI

Interoperable Spatial Information Model and Design Environment Based on ucR Technology
Yukihiko SHIGESADA Shinsuke KOBAYASHI Noboru KOSHIZUKA Ken SAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/01/01
Vol. E96-D  No. 1  pp. 51-63
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
spatial information system, ubiquitous computing, ubiquitous spatial infrastructure, spatial databases and GIS, web based services, 
 Summary | Full Text:PDF
UWB-IR Wireless Accurate Location System for Sensor Network
Kenichi MIZUGAKI Tatsuo NAKAGAWA Ryosuke FUJIWARA Shinsuke KOBAYASHI Noboru KOSHIZUKA Ken SAKAMURA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/05/01
Vol. E94-B  No. 5  pp. 1432-1437
Type of Manuscript:  PAPER
Category: Sensing
Keyword: 
UWB-IR, wireless location, TDOA, HDOP, 
 Summary | Full Text:PDF
0.7-GHz-Bandwidth DS-UWB-IR System for Low-Power Wireless Communications
Ryosuke FUJIWARA Akira MAEKI Kenichi MIZUGAKI Goichi ONO Tatsuo NAKAGAWA Takayasu NORIMATSU Masaru KOKUBO Masayuki MIYAZAKI Yasuyuki OKUMA Miki HAYAKAWA Shinsuke KOBAYASHI Noboru KOSHIZUKA Ken SAKAMURA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/02/01
Vol. E91-B  No. 2  pp. 518-526
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
impulse radio, LR-WPAN, UWB, wireless sensor networks, 
 Summary | Full Text:PDF
A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors
Shinsuke KOBAYASHI Kentaro MITA Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2586-2595
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Hardware/Software Codesign
Keyword: 
compiler generation, ASIP, design space exploration, 
 Summary | Full Text:PDF
Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Shinsuke KOBAYASHI Yoshinori TAKEUCHI Akira KITAJIMA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 748-754
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
multi-threading, very long instruction word (VLIW), instruction level parallelism, thread level parallelism, HW/SW co-design, 
 Summary | Full Text:PDF