Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 56

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 203

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 212

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 276

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 304

Warning: Undefined array key "abst" in /var/www/02search_html/bin/author.php on line 323
IEICE Trans

Shingo NAKAYA

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Shinya YAMASAKI Shingo NAKAYA Shin'ichi WAKABAYASHI Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2775-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
floorplanning, timing-driven layout, buffer insertion, wire sizing, simulated annealing, 
 Summary | Full Text:PDF