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IEICE Trans

Shigeru DATE

High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11  pp. 1641-1648
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
ASIC, CMOS, macrocell, memory, configurable, row sliceable, decoder, short design Turn-Around-Time (TAT), 
 Summary | Full Text:PDF
Hierarchical Module Generation Technique for a High Performance Memory Macrocell
Shigeru DATE Ken-ichi ENDO Mitsuyoshi NAGATANI Junzo YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Vol. E74-C  No. 4  pp. 938-945
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: ASIC
Keyword: 
 Summary | Full Text:PDF