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IEICE Trans

Satoshi NAKAMOTO

Full Chip Circuit/Substrate Macro Modeling Method Which Controls the Analysis Accuracy and CPU Time by Using Current Density
Mikiko Sode TANAKA Mikihiro KAJITA Naoya NAKAYAMA Satoshi NAKAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/02/01
Vol. E93-A  No. 2  pp. 448-455
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
substrate noise, power supply noise, substrate modeling, clock jitter, high speed, 
 Summary | Full Text:PDF