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IEICE Trans

Pietro NANNIPIERI

A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case
Pietro NANNIPIERI Gianmarco DINELLI Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/05/01
Vol. E102-A  No. 5  pp. 747-749
Type of Manuscript:  LETTER
Category: Communication Theory and Signals
Keyword: 
VLSI, multi-lane, high-speed, word re-ordering, SpaceFibre, 
 Summary | Full Text:PDF
VHDL Design of a SpaceFibre Routing Switch
Alessandro LEONI Pietro NANNIPIERI Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/05/01
Vol. E102-A  No. 5  pp. 729-731
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
SpaceFibre, SpaceWire, RoutingSwitch, satellite networks, FPGA, 
 Summary | Full Text:PDF
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution
Pietro NANNIPIERI Daniele DAVALLE Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2018/07/01
Vol. E101-A  No. 7  pp. 1120-1122
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
VLSI, 8b10b, parallel, encoding, 
 Summary | Full Text:PDF