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IEICE Trans

Osamu NAGASHIMA

A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
Satoru HANZAWA Hiromasa NODA Takeshi SAKATA Osamu NAGASHIMA Sadayuki MORITA Masanori ISODA Michiyo SUZUKI Sadayuki OHKUMA Kyoko MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1625-1633
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
clock-recovery circuit, timing adjuster, delay line, DDR SDRAM, 
 Summary | Full Text:PDF
Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design
Peter M. LEE Tsuyoshi SEO Kiyoshi ISE Atsushi HIRAISHI Osamu NAGASHIMA Shoji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/04/25
Vol. E81-C  No. 4  pp. 595-601
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carrier degradation, reliability, device lifetime, circuit simulation, SRAM, DRAM, 
 Summary | Full Text:PDF