A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs

Satoru HANZAWA  Hiromasa NODA  Takeshi SAKATA  Osamu NAGASHIMA  Sadayuki MORITA  Masanori ISODA  Michiyo SUZUKI  Sadayuki OHKUMA  Kyoko MURAKAMI  

IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.8   pp.1625-1633
Publication Date: 2002/08/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Optoelectronics
clock-recovery circuit,  timing adjuster,  delay line,  DDR SDRAM,  

Full Text: PDF>>
Buy this Article

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.