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IEICE Trans

Motoki OBATA

Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture
Keiji KIMURA Takeshi KODAKA Motoki OBATA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 570-579
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
chip multiprocessor, multigrain parallel processing, parallelizing compiler, 
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