IEICE Trans

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IEICE Trans

Morihiro KUGA

Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic Souhei TAKAGI Takuya KOJIMA Hideharu AMANO Morihiro KUGA Masahiro IIDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2024/12/01 Vol. E107-D No. 12 pp. 1476-1483 Type of Manuscript: PAPER Category: Computer System Keyword: SLM reconfigurable logic, run-length compression, FPGA,
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An eFPGA Generation Suite with Customizable Architecture and IDE Morihiro KUGA Qian ZHAO Yuya NAKAZATO Motoki AMAGASAKI Masahiro IIDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2023/03/01 Vol. E106-A No. 3 pp. 560-574 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA-IP, eFPGA, FPGA CAD, FPGA architecture, application-specific acceleration,
	Summary \| Full Text:PDF

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform Qian ZHAO Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2018/02/01 Vol. E101-D No. 2 pp. 335-343 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology and Platform Keyword: FPGA-as-a-service, hardware acceleration, open-source hardware,
	Summary \| Full Text:PDF

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core Motoki AMAGASAKI Yuki NISHITANI Kazuki INOUE Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2017/04/01 Vol. E100-D No. 4 pp. 633-644 Type of Manuscript: INVITED PAPER (Special Section on Award-winning Papers) Category: Keyword: fault tolerant, fault recovery, FPGA-IP,
	Summary \| Full Text:PDF

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC Motoki AMAGASAKI Qian ZHAO Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/02/01 Vol. E98-D No. 2 pp. 252-261 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: fault tolerant, FPGA, IP-core,
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FPGA Design Framework Combined with Commercial VLSI CAD Qian ZHAO Kazuki INOUE Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1602-1612 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: FPGA, CAD, routing,
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Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration Yoshihiro ICHINOMIYA Tsuyoshi KIMURA Motoki AMAGASAKI Morihiro KUGA Masahiro IIDA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2347-2356 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: FPGA, partial reconfiguration, fault-injection analysis, soft-error, dependability,
	Summary \| Full Text:PDF

Tradeoffs in Processor Design for Superscalar Architectures Kazuaki MURAKAMI Morihiro KUGA Oubong GWUN Shinji TOMITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1991/11/25 Vol. E74-D No. 11 pp. 3883-3893 Type of Manuscript: PAPER Category: Computer Systems Keyword:
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