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IEICE Trans

Mitsutoshi YAHARA

All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter
Mitsutoshi YAHARA Kuniaki FUJIMOTO Hirofumi SASAKI Takashi SHIBUYA Yoshinori HIGASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6  pp. 1527-1532
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
PLL, jitter, delay clock, lock-in range, digital, 
 Summary | Full Text:PDF
A Voltage Controlled Oscillator with Up Mode Type Miller-Integrator
Mitsutoshi YAHARA Kuniaki FUJIMOTO Hirofumi SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/12/01
Vol. E88-C  No. 12  pp. 2385-2387
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
Miller-integrator, NOR gate, astable multivibrator, voltage controlled oscillator, 
 Summary | Full Text:PDF
A Voltage Controlled Astable Multivibrator with Miller-Integrator
Hirofumi SASAKI Kuniaki FUJIMOTO Mitsutoshi YAHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/02/25
Vol. E78-A  No. 2  pp. 196-198
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Computer Aided Design)
Category: 
Keyword: 
miller integrator, astable multivibrator, voltage controlled oscillator, 
 Summary | Full Text:PDF