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IEICE Trans

Minkyu SONG

A 65 nm 1.2 V 7-bit 1 GSPS Folding-Interpolation A/D Converter with a Digitally Self-Calibrated Vector Generator
Daeyun KIM Minkyu SONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/07/01
Vol. E94-C  No. 7  pp. 1199-1205
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
folding, interpolation, A/D converter, self-calibration, offset error, 
 Summary | Full Text:PDF
Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit
Sanghoon HWANG Junho MOON Minkyu SONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/02/01
Vol. E91-C  No. 2  pp. 213-219
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
A/D converter, folding and interpolation architecture, averaging technique, 
 Summary | Full Text:PDF
A Fully Integrated Current-Steering 10-b CMOS D/A Converter with On-Chip Terminated Resistors
Sanghoon HWANG Minkyu SONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/12/01
Vol. E87-C  No. 12  pp. 2179-2185
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
DAC, internal termination resistors, current steering, current switch, self-calibrated current bias, 
 Summary | Full Text:PDF
Design of a Conditional Sign Decision Booth Encoder for a High Performance 3232-Bit Digital Multiplier
Minkyu SONG Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/09/01
Vol. E85-C  No. 9  pp. 1709-1717
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
3232-bit multiplier, conditional sign decision Booth encoder, compound logic, 9-2 compressor, 64-bit conditional select adder, 
 Summary | Full Text:PDF
A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder
Sanghoon JOO Minkyu SONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1554-1561
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits)
Category: 
Keyword: 
folding/interpolation ADC, analog latch, digital encoder, delay error correction, 
 Summary | Full Text:PDF
Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic
Minkyu SONG Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/11/25
Vol. E81-C  No. 11  pp. 1740-1749
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
power saved pass-transistor logic (PSPL), low power, regenerative feedback, 5454-bit multiplier, 7-bit serial counter, 
 Summary | Full Text:PDF
Power Optimization for Data Compressors Based on a Window Detector in a 5454 Bit Multiplier
Minkyu SONG Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7  pp. 1016-1024
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
a parallel structured architecture, low power data compressors, a Window Detector, 
 Summary | Full Text:PDF