IEICE Trans - A 65 nm 1.2 V 7-bit 1 GSPS Folding-Interpolation A/D Converter with a Digitally Self-Calibrated Vector Generator

A 65 nm 1.2 V 7-bit 1 GSPS Folding-Interpolation A/D Converter with a Digitally Self-Calibrated Vector Generator

Daeyun KIM
Minkyu SONG

Publication
IEICE TRANSACTIONS on Electronics Vol.E94-C No.7 pp.1199-1205
Publication Date: 2011/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1199
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword:
folding, interpolation, A/D converter, self-calibration, offset error,

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Summary:
In this paper, a 65 nm 1.2 V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65 nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87 mm² and the power consumption is about 110 mW with a 1.2 V power supply. The measured SNDR is about 39.1 dB when the input frequency is 250 MHz at a 1 GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.