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Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's
Takeshi HAMAMOTO Yoshikazu MOROOKA Mikio ASAKURA Hideyuki OZAKI | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Vol. E79-C
No. 7
pp. 1003-1012
Type of Manuscript:
Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
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A Well-Synchronized Sensing/Equalizing Method for Sub-1.0-V Operating Advanced DRAM's
Tsukasa OOISHI Mikio ASAKURA Shigeki TOMISHIMA Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/05/25
Vol. E77-C
No. 5
pp. 762-770
Type of Manuscript:
Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Category:
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Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's
Mikio ASAKURA Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1992/04/25
Vol. E75-C
No. 4
pp. 495-500
Type of Manuscript:
Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
Category:
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Mechanism of Bit Line Mode Soft Error for DRAM
Mikio ASAKURA Yoshio MATSUDA Katsuhiro TSUKAMOTO Kazuyasu FUJISHIMA Tsutomu YOSHIHARA | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1987/11/25
Vol. E70-E
No. 11
pp. 1060-1061
Type of Manuscript:
Special Section LETTER (Special Issue: Papers from 1987 National Conference on Semicondutor Devices and Materials IEICE)
Category: Semiconductor Devices
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