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IEICE Trans

Masato IKEBE

Three Dimensional FPGA Architecture with Fewer TSVs
Motoki AMAGASAKI Masato IKEBE Qian ZHAO Masahiro IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2018/02/01
Vol. E101-D  No. 2  pp. 278-287
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Device and Architecture
Keyword: 
three dimensional IC, 3D-FPGA, power estimation, face-down/face-up stacking, 
 Summary | Full Text:PDF