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IEICE Trans

Masashi SASAHARA

200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology
Tatsuo TERUYAMA Tetsuo KAMADA Masashi SASAHARA Shardul KAZI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 235-242
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
microprocessor, MIPS, SIMD, tiling, network, 
 Summary | Full Text:PDF