200 MHz 128 Bit Synthesizable Core with SIMD Extension and Its Design Methodology

Tatsuo TERUYAMA  Tetsuo KAMADA  Masashi SASAHARA  Shardul KAZI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.2   pp.235-242
Publication Date: 2002/02/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
microprocessor,  MIPS,  SIMD,  tiling,  network,  

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Summary: 
The strong demand for complex and high performance system-on-a-chip requires high performance microprocessor core and quick turn around design methodology. We have developed 128-bit synthesizable core processor and tile based quick turn around design methodology. It is 200 MHz MIPS compatible processor with 128-bit SIMD extension and is targeted for consumer electronics. We also developed an ASSP including the processor core, SDRAM controller, 2 PCI and 2 MAC mainly for network applications. For SOC development, we developed a tile based design methodology aiming at quick design convergence. The initial RTL design is synthesized and partitioned to several tiles by in-house tiling tool. It promises quick turn around from RTL design to tape out using the concurrency of the back-end design.