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A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A
No. 3
pp. 321-329
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
FPGA, technology mapping, layout, path delay, performance optimization, | | | Summary | Full Text:PDF | |
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A VLSI Geometrical Design Rule Verification Accelerated by CAM-Based Hardware Engine
Tetsuro TAKIZAWA Kazuto KUBOTA Masao SATO Tatsuo OHTSUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1991/10/25
Vol. E74-A
No. 10
pp. 3072-3077
Type of Manuscript:
Special Section PAPER (Special Issue on JTC-CSCC '90)
Category: VLSI Design Technology
Keyword:
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