Keyword : layout design

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits
Kazuyoshi TAKAGI Nobutaka KITO Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3 ; pp. 149-156
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single-flux-quantum circuit, design methodology, circuit description, logic design, layout design, design verification, 
 Summary | Full Text:PDF
An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio
Susumu KOBAYASHI Naoshi DOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 492-499
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
decoupling capacitance, power supply noise, power dissipation, layout design, simulation, 
 Summary | Full Text:PDF
A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths
Susumu KOBAYASHI Masato EDAHIRO Mikio KUBO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2499-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSI CAD, scan-chain, layout design, design for testability, 
 Summary | Full Text:PDF
Efficient Routability Checking for Global Wires in Planar Layouts
Naoyuki ISO Yasushi KAWAGUCHI Tomio HIRATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1878-1882
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
layout design, routability, routing, 
 Summary | Full Text:PDF
A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1795-1806
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, transport processing, layout design, placement and routing, performance optimization, circuit delay, 
 Summary | Full Text:PDF
A Balanced-Mesh Clock Routing Technique for Performance Improvement
Hidenori SATO Hiroaki MATSUDA Akira ONOZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/08/25
Vol. E80-A  No. 8 ; pp. 1489-1495
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LSI, CAD, layout design, clock skew, partitioning, routing, MPEG2, 
 Summary | Full Text:PDF
Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout
Nozumu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2140-2150
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, transport processing, layout design, placement and routing network flow, 
 Summary | Full Text:PDF
Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2028-2038
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, look up table, technology mapping, layout design, placement, global routing, 
 Summary | Full Text:PDF
Optimal Constraint Graph Generation Algorithm for Layout Compaction Using Enhanced Plane-Sweep Method
Toru AWASHIMA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4 ; pp. 507-512
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computer aided design, LSI design technology, layout design, compaction, plane-sweep method, 
 Summary | Full Text:PDF