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IEICE Trans

Masanori ISODA

A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
Satoru HANZAWA Hiromasa NODA Takeshi SAKATA Osamu NAGASHIMA Sadayuki MORITA Masanori ISODA Michiyo SUZUKI Sadayuki OHKUMA Kyoko MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8  pp. 1625-1633
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
clock-recovery circuit, timing adjuster, delay line, DDR SDRAM, 
 Summary | Full Text:PDF
Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's
Yoshinobu NAKAGOME Kiyoo ITOH Masanori ISODA Kan TAKEUCHI Masakazu AOKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 754-759
Type of Manuscript:  Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category: 
Keyword: 
 Summary | Full Text:PDF