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IEICE Trans

Masa-aki FUKASE

Signal Propagation Delay Model in Vertically Stacked Chips
Nanako NIIOKA Masayuki WATANABE Masa-aki FUKASE Masashi IMAI Atsushi KUROKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12  pp. 2614-2624
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
3-D IC, delay, through silicon via, sensitivity analysis, 
 Summary | Full Text:PDF