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IEICE Trans

Kota ANDO

Extending Binary Neural Networks to Bayesian Neural Networks with Probabilistic Interpretation of Binary Weights
Taisei SAITO Kota ANDO Tetsuya ASAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2024/08/01
Vol. E107-D  No. 8  pp. 949-957
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: 
Keyword: 
Bayseian neural network, Binary connect, quantization, memory reduction, uncertainty estimation, 
 Summary | Full Text:PDF
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems
Daiki OKONOGI Satoru JIMBO Kota ANDO Thiem Van CHU Jaehoon YU Masato MOTOMURA Kazushi KAWAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2023/12/01
Vol. E106-D  No. 12  pp. 1969-1978
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
combinatorial optimization, Ising model, annealing processor, parallel annealing algorithm, stochastic cellular automata, 
 Summary | Full Text:PDF
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers
Satoru JIMBO Daiki OKONOGI Kota ANDO Thiem Van CHU Jaehoon YU Masato MOTOMURA Kazushi KAWAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2022/12/01
Vol. E105-D  No. 12  pp. 2019-2031
Type of Manuscript:  Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
combinatorial optimization, Ising model, simulated annealing, integer encoding, quadratic knapsack problem, 
 Summary | Full Text:PDF
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
Kota ANDO Kodai UEYOSHI Yuka OBA Kazutoshi HIROSE Ryota UEMATSU Takumi KUDO Masayuki IKEBE Tetsuya ASAI Shinya TAKAMAEDA-YAMAZAKI Masato MOTOMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2341-2353
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
neural network, dithering, error diffusion, FPGA, hardware-oriented neural network algorithm, 
 Summary | Full Text:PDF