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IEICE Trans

Kengo NAKATA

Quantization Strategy for Achieving Low-Cost, Accurate, Pareto-Optimal Convolutional Neural Networks Based on Analysis of Quantized Weight Parameters
Kengo NAKATA Daisuke MIYASHITA Asuka MAKI Fumihiko TACHIBANA Shinichi SASAKI Jun DEGUCHI Ryuichi FUJIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/11/01
Vol. E108-A  No. 11  pp. 1526-1535
Type of Manuscript:  PAPER
Category: Neural Networks and Bioengineering
Keyword: 
deep learning, convolutional neural networks, quantization, pruning, mixed-precision computing, 
 Summary | Full Text:PDF
Accelerating CNN Inference with an Adaptive Quantization Method Using Computational Complexity-Aware Regularization
Kengo NAKATA Daisuke MIYASHITA Jun DEGUCHI Ryuichi FUJIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/02/01
Vol. E108-A  No. 2  pp. 149-159
Type of Manuscript:  PAPER
Category: Neural Networks and Bioengineering
Keyword: 
deep learning, convolutional neural networks, inference, quantization, mixed-precision computing, 
 Summary | Full Text:PDF
Weight Compression MAC Accelerator for Effective Inference of Deep Learning
Asuka MAKI Daisuke MIYASHITA Shinichi SASAKI Kengo NAKATA Fumihiko TACHIBANA Tomoya SUZUKI Jun DEGUCHI Ryuichi FUJIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2020/10/01
Vol. E103-C  No. 10  pp. 514-523
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: Integrated Electronics
Keyword: 
deep learning, convolutional neural network, quantization, variable bit width, post-training, inference, accelerator, processor, FPGA, 
 Summary | Full Text:PDF
A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS
Hanli LIU Teerachot SIRIBURANON Kengo NAKATA Wei DENG Ju Ho SON Dae Young LEE Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2018/04/01
Vol. E101-C  No. 4  pp. 187-196
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
5G communications, CMOS, 28GHz, fractional-N frequency synthesizer, phase noise, spur, 
 Summary | Full Text:PDF
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI
Dongsheng YANG Tomohiro UENO Wei DENG Yuki TERASHIMA Kengo NAKATA Aravind Tharayil NARAYANAN Rui WU Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6  pp. 632-640
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
AD-PLL, synthesizable, stochastic TDC, standard cell, automatic place-and-route, 
 Summary | Full Text:PDF