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IEICE Trans

Kazuaki HORI

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator
Naoya AZUMA Shunsuke SHIMAZAKI Noriyuki MIURA Makoto NAGATA Tomomitsu KITAMURA Satoru TAKAHASHI Motoki MURAKAMI Kazuaki HORI Atsushi NAKAMURA Kenta TSUKAMOTO Mizuki IWANAMI Eiji HANKUI Sho MUROGA Yasushi ENDO Satoshi TANAKA Masahiro YAMAGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6  pp. 546-556
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
substrate coupling, power delivery network, noise interference, wireless communication, 
 Summary | Full Text:PDF