Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator

Naoya AZUMA  Shunsuke SHIMAZAKI  Noriyuki MIURA  Makoto NAGATA  Tomomitsu KITAMURA  Satoru TAKAHASHI  Motoki MURAKAMI  Kazuaki HORI  Atsushi NAKAMURA  Kenta TSUKAMOTO  Mizuki IWANAMI  Eiji HANKUI  Sho MUROGA  Yasushi ENDO  Satoshi TANAKA  Masahiro YAMAGUCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E97-C   No.6   pp.546-556
Publication Date: 2014/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E97.C.546
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
substrate coupling,  power delivery network,  noise interference,  wireless communication,  

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Summary: 
Substrate noise coupling in RF receiver front-end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65nm CMOS technology. A CMOS digital noise emulator injects high-order harmonic noises in a silicon substrate and induces in-band spurious tones in an RF receiver on the same chip through substrate noise interference. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compared with the measurements. The interference of substrate noise at the 17th harmonics of 124.8MHz — the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1GHz.