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IEICE Trans

Kasho YAMAMOTO

FPGA-Based Annealing Processor with Time-Division Multiplexing
Kasho YAMAMOTO Masayuki IKEBE Tetsuya ASAI Masato MOTOMURA Shinya TAKAMAEDA-YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2019/12/01
Vol. E102-D  No. 12  pp. 2295-2305
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer System
Keyword: 
ising model, annealing processor, simulated annealing, 
 Summary | Full Text:PDF