Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme Koichi MORIKAWAJiro IDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/25 Vol. E79-CNo. 12pp. 1713-1719 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: local wiring, junction capacitance, embedded SRAM, coupling noise,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/04/25 Vol. E76-CNo. 4pp. 525-531 Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies) Category: Device Technology Keyword: CMOS, LDD, hot-carrier-reliability, multiplier,