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IEICE Trans

How-Rern LIN

Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs
Tsung-Yi WU Tzi-Wei KAO How-Rern LIN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2581-2589
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
clock scheme, globally asynchronous locally synchronous, IR drop, Network-on-Chip, 
 Summary | Full Text:PDF
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
How-Rern LIN Wei-Hao CHIU Tsung-Yi WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4  pp. 386-390
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
leakage power, leakage tolerance, high performance, domino logic, 
 Summary | Full Text:PDF