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IEICE Trans

Hiroshi NINOMIYA

Investigation of DNN-Based Audio-Visual Speech Recognition
Satoshi TAMURA Hiroshi NINOMIYA Norihide KITAOKA Shin OSUGA Yurie IRIBE Kazuya TAKEDA Satoru HAYAMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/10/01
Vol. E99-D  No. 10  pp. 2444-2451
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Machine Learning for Spoken Language Processing)
Category: Acoustic modeling
Keyword: 
audio-visual speech recognition, deep neural network, Deep Bottleneck Feature, multi-stream HMM, 
 Summary | Full Text:PDF
Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5  pp. 1051-1058
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuit, ambipolar double-gate devices, dynamic logic, CNTFETs, 
 Summary | Full Text:PDF
Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs
Hiroshi NINOMIYA Manabu KOBAYASHI Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2  pp. 675-678
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
reconfigurable logic circuit design, ambipolar device, double-gate CNTFET, binary decision diagram, arithmetic logic unit, 
 Summary | Full Text:PDF
Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7  pp. 1642-1644
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuit, ambipolar double-gate devices, dynamic logic, CNTFETs, 
 Summary | Full Text:PDF
Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram
Hiroshi NINOMIYA Manabu KOBAYASHI Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1  pp. 356-359
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic design, ambipolar device, double gate CNTFET, binary decision diagram, 
 Summary | Full Text:PDF
Design Method of Neural Networks for Limit Cycle Generator by Linear Programming
Teru YONEYAMA Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 688-692
Type of Manuscript:  LETTER
Category: Neural Networks and Bioengineering
Keyword: 
neural network, limit cycle generator, linear programming, synaptic weights, analog electronic circuits, 
 Summary | Full Text:PDF
A Fast Neural Network Simulator for State Transition Analysis
Atsushi KAMO Hiroshi NINOMIYA Teru YONEYAMA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9  pp. 1796-1801
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
stepwise constant method, multivalued neural network, ASSIST, state transition analysis, 
 Summary | Full Text:PDF
A Fast Algorithm for Spatiotemporal Pattern Analysis of Neural Networks with Multivalued Logic
Hiroshi NINOMIYA Atsushi KAMO Teru YONEYAMA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/09/25
Vol. E81-A  No. 9  pp. 1847-1852
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: Neural Networks
Keyword: 
continuous-time neural networks, multivalued logic, stepwise constant function, spatiotemporal pattern analysis, 
 Summary | Full Text:PDF
A Neuro-Based Optimization Algorithm for Rectangular Puzzles
Hiroyuki YAMAMOTO Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6  pp. 1113-1118
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Neural Networks
Keyword: 
cubic puzzles, tiling problem, 3-D neuro array, analog neural network, 
 Summary | Full Text:PDF
A Neuro-Based Optimization Algorithm for Three Dimensional Cylindric Puzzles
Hiroyuki YAMAMOTO Takeshi NAKAYAMA Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6  pp. 1049-1054
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
cylindrical puzzles, tiling problem, polyomino, analog neural network, omega function heuristic, 
 Summary | Full Text:PDF
Neural Networks for Digital Sequential Circuits
Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12  pp. 2112-2115
Type of Manuscript:  LETTER
Category: Neural Networks
Keyword: 
Hopfield neural networks, optimization problem, digital sequential circuits, energy function, global convergence, 
 Summary | Full Text:PDF
A Neural Net Approach to Discrete Walsh Transform
Takeshi KAMIO Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11  pp. 1882-1886
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
neural network, linear programming problem, energy function, discrete Walsh transform, Walsh function, Hadamard matrix, 
 Summary | Full Text:PDF
Design and Simulation of Neural Network Digital Sequential Circuits
Hiroshi NINOMIYA Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6  pp. 968-976
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Analog Circuits and Signal Processing
Keyword: 
Hopfield neural networks, optimization problem, digital sequential circuits, energy function, global convergence, 
 Summary | Full Text:PDF