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IEICE Trans

Hironori UCHIKAWA

Improving Multi-Level Flash Memory with SHare Coding for Faster and More Efficient Data Access
Hironori UCHIKAWA Noboru SHIBATA Taira SHIBUYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A  No. 3  pp. 396-405
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: 
Keyword: 
flash memory, multi-level cell, coding, read threshold, 
 Summary | Full Text:PDF
Double-Stack Erasure-Filled Channel and Level-By-Level Error Correction
Hironori UCHIKAWA Manabu HAGIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/03/01
Vol. E108-A  No. 3  pp. 376-383
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory and Techniques
Keyword: 
racetrack memory, deletion channel, symmetric information rate, error correction, LDPC codes, 
 Summary | Full Text:PDF
Joint BCH and XOR Decoding for Solid State Drives
Naoko KIFUNE Hironori UCHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2023/10/01
Vol. E106-A  No. 10  pp. 1322-1329
Type of Manuscript:  PAPER
Category: Coding Theory
Keyword: 
RAID, XOR, BCH, error-correcting codes, storage system, flash memory, 
 Summary | Full Text:PDF
Spatially Coupled Protograph-Based LDPC Codes for Decode-and-Forward in Erasure Relay Channel
Hironori UCHIKAWA Kenta KASAI Kohichi SAKANIWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2127-2134
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
spatially coupled codes, protograph-based LDPC codes, relay, erasure channel, 
 Summary | Full Text:PDF
Design and Performance of Rate-Compatible Non-binary LDPC Convolutional Codes
Hironori UCHIKAWA Kenta KASAI Kohichi SAKANIWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2135-2143
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
non-binary LDPC codes, LDPC convolutional codes, rate-compatibility, 
 Summary | Full Text:PDF
Optimum Soft-Output of Autoregressive Detector for Offtrack Interference in LDPC-Coded Perpendicular Magnetic Recording
Kohsuke HARADA Haruka OBATA Hironori UCHIKAWA Kenji YOSHIDA Yuji SAKAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/11/01
Vol. E93-A  No. 11  pp. 1966-1975
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
perpendicular magnetic recording, offtrack interference, autoregressive detector, LDPC codes, 
 Summary | Full Text:PDF
Complexity-Reducing Algorithm for Serial Scheduled Min-Sum Decoding of LDPC Codes
Hironori UCHIKAWA Kohsuke HARADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10  pp. 2411-2417
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
low-density parity-check codes, min-sum decoding, serial scheduling, and complexity, 
 Summary | Full Text:PDF
Secure Download System Based on Software Defined Radio Composed of FPGAs
Hironori UCHIKAWA Kenta UMEBAYASHI Ryuji KOHNO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/12/01
Vol. E85-B  No. 12  pp. 2601-2609
Type of Manuscript:  Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
download, security, field programmable gate array (FPGA), software defined radio (SDR), 
 Summary | Full Text:PDF