Keyword : field programmable gate array (FPGA)


Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh
Takayuki AKAMINE Mohamad Sofian ABU TALIP Yasunori OSANA Naoyuki FUJITA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5 ; pp. 1225-1234
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
computational fluid dynamics (CFD)field programmable gate array (FPGA)scientific computationsreconfigurable hardwareout-of-order system
 Summary | Full Text:PDF

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA
Mohamad Sofian ABU TALIP Takayuki AKAMINE Yasunori OSANA Naoyuki FUJITA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10 ; pp. 2369-2376
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
computational fluid dynamics (CFD)field programmable gate array (FPGA)scientific computationsreconfigurable hardwarepartial reconfiguration
 Summary | Full Text:PDF

FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine
Kazuya ZAITSU Koji YAMAMOTO Yasuto KURODA Kazunari INOUE Shingo ATA Ikuo OKA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/07/01
Vol. E95-B  No. 7 ; pp. 2306-2314
Type of Manuscript:  PAPER
Category: Network System
Keyword: 
IP routeraddress lookupternary content addressable memory (TCAM)power consumptionfield programmable gate array (FPGA)circuit design
 Summary | Full Text:PDF

Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic
Hongge LI Yoshihiro HAYAKAWA Shigeo SATO Koji NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/09/01
Vol. E89-D  No. 9 ; pp. 2572-2578
Type of Manuscript:  PAPER
Category: Biocybernetics, Neurocomputing
Keyword: 
inverse function delayed modelassociative memoryfield programmable gate array (FPGA)stochastic logic
 Summary | Full Text:PDF

Prototype Implementation of Real-Time ML Detectors for Spatial Multiplexing Transmission
Toshiaki KOIKE Yukinaga SEKI Hidekazu MURATA Susumu YOSHIDA Kiyomichi ARAKI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/03/01
Vol. E89-B  No. 3 ; pp. 845-852
Type of Manuscript:  PAPER
Category: Wireless Communication Technologies
Keyword: 
multiple-input multiple-output (MIMO)spatial multiplexingmaximum-likelihood detection (MLD)field programmable gate array (FPGA)real-time MIMO detector
 Summary | Full Text:PDF

Secure Download System Based on Software Defined Radio Composed of FPGAs
Hironori UCHIKAWA Kenta UMEBAYASHI Ryuji KOHNO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/12/01
Vol. E85-B  No. 12 ; pp. 2601-2609
Type of Manuscript:  Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
downloadsecurityfield programmable gate array (FPGA)software defined radio (SDR)
 Summary | Full Text:PDF

Look Up Table Compaction Based on Folding of Logic Functions
Shinji KIMURA Atsushi ISHII Takashi HORIYAMA Masaki NAKANISHI Hirotsugu KAJIHARA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2701-2707
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
field programmable gate array (FPGA)LUT architecturereconfigurable logic
 Summary | Full Text:PDF

A General Framework to Use Various Decomposition Methods for LUT Network Synthesis
Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2915-2922
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
functional decompositionalgebraic decompositionfield programmable gate array (FPGA)look-up table (LUT)
 Summary | Full Text:PDF

A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
Chi-Chou KAO Yen-Tai LAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2690-2696
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: FPGA Systhesis
Keyword: 
technology mappingroutabilitymin-cutfield programmable gate array (FPGA)
 Summary | Full Text:PDF

Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data
Abderrahim DOUMAR Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5 ; pp. 1104-1115
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
defect tolerancefault tolerancefield programmable gate array (FPGA)shifting configurations datayield improvement
 Summary | Full Text:PDF

Fast Testable Design for SRAM-Based FPGAs
Abderrahim DOUMAR Toshiaki OHMAMEUDA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5 ; pp. 1116-1127
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
field programmable gate array (FPGA)testingdesign for testingshifting configurations
 Summary | Full Text:PDF