Symbolic Model Checking of Deadlock Free Property of Task Control Architecture Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-DNo. 10pp. 1579-1586 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Verification Keyword: verification, symbolic model checking, deadlock, robot control program, concurrent process,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-DNo. 10pp. 1465-1465 Type of Manuscript: FOREWORD Category: Keyword:
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/25 Vol. E80-DNo. 1pp. 57-62 Type of Manuscript: Special Section PAPER (Special Issue on Fault-Tolerant Computing) Category: Verification Keyword: formal verification, totally self-checking, fault tolerance, binary decision diagram,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/25 Vol. E78-DNo. 7pp. 796-801 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: formal verification, real-time system, temporal logic,
An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System Kazuo KAWAKUBOHiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-DNo. 7pp. 763-770 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: fail-safe, fault tolerance, formal verification, temporal logic,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-ANo. 10pp. 1220-1229 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: design verification, sequential machines, temporal logic, model checking, binary decision diagram,