Keyword : temporal logic

A Model Checking Method of Soundness for Workflow Nets
Munenori YAMAGUCHI Shingo YAMAGUCHI Minoru TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/11/01
Vol. E92-A  No. 11 ; pp. 2723-2731
Type of Manuscript:  Special Section PAPER (Special Section on Theory of Concurrent Systems and its Applications)
Category: 
Keyword: 
model checking, temporal logic, workflow nets, asymmetric choice, Woflan, 
 Summary | Full Text:PDF
A Tableau Construction Approach to Control Synthesis of FSMs Using Simulation Relations
Yoshisato SAKAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4 ; pp. 836-846
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
temporal logic, tableau, control synthesis, simulation relation, 
 Summary | Full Text:PDF
ASADAL/PROVER: A Toolset for Verifying Temporal Properties of Real-Time System Specifications in Statechart
Kwang-Il KO Kyo C. KANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/25
Vol. E82-D  No. 2 ; pp. 398-411
Type of Manuscript:  PAPER
Category: Sofware System
Keyword: 
requirement engineering, CASE, Statechart, temporal logic, temporal property verification techniques, 
 Summary | Full Text:PDF
New Generation Database Technologies for Collaborative Work Support and Spatio-Temporal Data Management
Yoshifumi MASUNAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/01/25
Vol. E82-D  No. 1 ; pp. 45-53
Type of Manuscript:  REVIEW PAPER
Category: 
Keyword: 
new generation database, collaborative work support, CSCW, virtual reality, spatio-temporal database, GIS, spatio-temporal index, temporal logic, view, multimedia database, VRML, WWW, internet, object-oriented database, 
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A Topological Framework of Stepwise Specification for Concurrent Systems
Toshihiko ANDO Kaoru TAKAHASHI Yasushi KATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/11/25
Vol. E79-A  No. 11 ; pp. 1760-1767
Type of Manuscript:  Special Section PAPER (Special Section on Description Models for Concurrent Systems and Their Applications)
Category: 
Keyword: 
stepwise specification, concurrent system, topology, abstract level of description technique, temporal logic, 
 Summary | Full Text:PDF
A Statically Typed, Temporal Object-Oriented Database Technology
Suad ALAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/11/25
Vol. E78-D  No. 11 ; pp. 1469-1476
Type of Manuscript:  Special Section PAPER (Special Issue on Advanced Database Technologies)
Category: Model
Keyword: 
object-oriented, type technology, temporal logic, reflection, 
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Temporal Verification of Real-Time Systems
Sérgio V. CAMPOS Edmund M. CLARKE Wilfredo MARRERO Marius MINEA Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 796-801
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
formal verification, real-time system, temporal logic, 
 Summary | Full Text:PDF
An Application of Regular Temporal Logic to Verification of Fail-Safeness of a Comparator for Redundant System
Kazuo KAWAKUBO Hiromi HIRAISHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fail-safe, fault tolerance, formal verification, temporal logic, 
 Summary | Full Text:PDF
An Acyclic Expansion-Based Protocol Verification for Communications Software
Hironori SAITO Yoshiaki KAKUDA Toru HASEGAWA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1992/10/25
Vol. E75-B  No. 10 ; pp. 998-1007
Type of Manuscript:  Special Section PAPER (Special Issue on Communication Software Technologies)
Category: 
Keyword: 
communications software, communication protocol, protocol verification, finite state machine, acyclic expansion algorithm, temporal logic, 
 Summary | Full Text:PDF
A Petri-Net-Based Programming Environment and Its Design Methodology for Cooperating Discrete Event Systems
Naoshi UCHIHIRA Mikako ARAMI Shinichi HONIDEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1335-1347
Type of Manuscript:  Special Section PAPER (Special Section on Application of Petri Nets to Concurrent System Design)
Category: 
Keyword: 
high level petri net, cooperating discrete event system, concurrent program, design methodology, program synthesis, program verification, temporal logic, programming environment, 
 Summary | Full Text:PDF
Net-Oriented Analysis and Design
Shinichi HONIDEN Naoshi UCHIHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1317-1325
Type of Manuscript:  INVITED PAPER (Special Section on Application of Petri Nets to Concurrent System Design)
Category: 
Keyword: 
petri nets, state transition didgram, data flow diagram, algebraic specification, temporal logic, object-oriented analysis and design, CASE, 
 Summary | Full Text:PDF
Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic
Kiyoharu HAMAGUCHI Hiromi HIRAISHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1220-1229
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
design verification, sequential machines, temporal logic, model checking, binary decision diagram, 
 Summary | Full Text:PDF
Compositional Synthesis for Cooperating Discrete Event Systems from Modular Temporal Logic Specifications
Naoshi UCHIHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 380-391
Type of Manuscript:  Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
cooperating discrete event system, temporal logic, compositional program synthesis, state explosion problem, 
 Summary | Full Text:PDF
A Study of Aspect Calculus
Kazuo HASHIMOTO Tohru ASAMI Seiichi YAMAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 436-450
Type of Manuscript:  PAPER
Category: Foundations of Artificial Intelligence and Knowledge Processing
Keyword: 
aspect, tense, temporal logic, formal semantics, 
 Summary | Full Text:PDF