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IEICE Trans

Hiroko TASHIRO

Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications
Kouji TSUNODA Akira SATO Hiroko TASHIRO Toshiro NAKANISHI Hitoshi TANAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 608-613
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
system-on-a-chip, embedded RAM, direct tunneling, tunnel oxide, gate depletion, 
 Summary | Full Text:PDF