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IEICE Trans

Henry BLOCK

FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm
Henry BLOCK Tsutomu MARUYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/02/01
Vol. E100-D  No. 2  pp. 256-264
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FPGA, hardware acceleration, phylogenetic tree reconstruction, maximum parsimony, 
 Summary | Full Text:PDF