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IEICE Trans

Guido MATRELLA

A Custom VLSI Architecture for the Solution of FDTD Equations
Pisana PLACIDI Leonardo VERDUCCI Guido MATRELLA Luca ROSELLI Paolo CIAMPOLINI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Vol. E85-C  No. 3  pp. 572-577
Type of Manuscript:  Special Section PAPER (Special Issue on Signals, Systems and Electronics Technology)
Category: Circuit
Keyword: 
FDTD method, digital arithmetic, very-large scale integration, VHDL language, 
 Summary | Full Text:PDF