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A Custom VLSI Architecture for the Solution of FDTD Equations
Pisana PLACIDI Leonardo VERDUCCI Guido MATRELLA Luca ROSELLI Paolo CIAMPOLINI
IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Signals, Systems and Electronics Technology)
FDTD method, digital arithmetic, very-large scale integration, VHDL language,
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In this paper, characteristics of a digital system dedicated to the fast execution of the FDTD algorithm, widely used for electromagnetic simulation, are presented. Such system is conceived as a module communicating with a host personal computer via a PCI bus, and is based on a VLSI ASIC, which implements the "field-update" engine. The system structure is defined by means of a hardware description language, allowing to keep high-level system specification independent of the actual fabrication technology. A virtual implementation of the system has been carried out, by mapping such description in a standard-cell style on a commercial 0.35 µm technology. Simulations show that significant speed-up can be achieved, with respect to state-of-the-art software implementations of the same algorithm.