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IEICE Trans

Eijiro SASSA

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution
Shimpei SATO Eijiro SASSA Yuta UKON Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Vol. E102-A  No. 12  pp. 1760-1769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
circuit design, variable-latency circuit, speculative execution, general-synchronous circuit, timing-error detection, 
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