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IEICE Trans

Edgar HOLMANN

A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor
Akira YAMADA Toyohiko YOSHIDA Tetsuya MATSUMURA Shin-ichi URAMOTO Koji TSUCHIHASHI Edgar HOLMANN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9  pp. 1382-1390
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
multimedia processor, media processor, VLIW, MPEG, microprocessor, 
 Summary | Full Text:PDF
A 2 V 250 MHz VLIW Multimedia Processor
Toyohiko YOSHIDA Akira YAMADA Edgar HOLMANN Hidehiro TAKATA Atsushi MOHRI Yukihiko SHIMAZU Kiyoshi NAKAKIMURA Keiichi HIGASHITANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5  pp. 651-660
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
multimedia processor, media processor, VLIW, MPEG, AC-3, microprocessor, 
 Summary | Full Text:PDF