A 2 V 250 MHz VLIW Multimedia Processor

Toyohiko YOSHIDA  Akira YAMADA  Edgar HOLMANN  Hidehiro TAKATA  Atsushi MOHRI  Yukihiko SHIMAZU  Kiyoshi NAKAKIMURA  Keiichi HIGASHITANI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.5   pp.651-660
Publication Date: 1998/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
multimedia processor,  media processor,  VLIW,  MPEG,  AC-3,  microprocessor,  

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Summary: 
A dual-issue VLIW processor, running at 250 MHz, is enhanced with multimedia instructions for a sustained peak performance of 1000MOPS. The multimedia processor integrates 300 K transistors in an 8 mm2 core area and it is fabricated onto a 6 mm6. 2 mm chip with 32 kB instruction and 32 kB data RAMs in a 0. 3-micrometer, four-layer metal CMOS process. It consumes 1. 2 W at 2. 0 V running at 250 MHz. The VLIW processor achieves a speed-up of more than 4 times over a single-issue RISC for MPEG video block decoding. A decoder implemented on the multimedia processor with a small amount of dedicated hardware, such as the Huffman decoder and a DMA controller will decode the worst case 88 video block data in 754 cycles, leading to a real-time MPEG-2 system, video, and audio decoding system.