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IEICE Trans

Bongjin KIM

Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division
Bongjin KIM In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/07/01
Vol. E96-B  No. 7  pp. 1772-1779
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
low-density parity-check (LDPC) codes, multi-mode decoder, low-area architecture, stride scheduling, 
 Summary | Full Text:PDF