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IEICE Trans

Alberto Palacios PAWLOVSKY

Partial Product Generator with Embedded Booth-Encoding
Alberto Palacios PAWLOVSKY Makoto HANAWA Kenji KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12  pp. 1793-1795
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
partial product generator, Booth-encoding, multiplier, Double Pass-transistor Logic (DPL), modified Booth's algorithm, 
 Summary | Full Text:PDF
Verification of Register Transfer Level (RTL) Designs
Alberto Palacios PAWLOVSKY Sachio NAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6  pp. 785-791
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
fault analysis, testing, verification, hardware description languages, regular expressions, directed graphs, 
 Summary | Full Text:PDF
A 1000 MIPS Superscalar Processor and Its Fault Tolerant Design
Alberto Palacios PAWLOVSKY Makoto HANAWA Osamu NISHII Tadahiko NISHIMUKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10  pp. 1212-1222
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: RISC Technologies
Keyword: 
superscalar processor, multiprocessor system, BiCMOS devices, fault-tolerance, concurrent fault detection, 
 Summary | Full Text:PDF